---------------------------------------------------------------------------
-- Company     : EIA / HTA 
-- Author      : Yves Peissard <ypeissard@gmail.com>
-- 
-- Creation Date : 23/04/2009
-- File          : buttonHandler.vhdl
--
-- Abstract : This is the testbench file for the buttonHandler block
--            of the iTimer project.
--            
-- 
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity buttonHandler_tb is
end buttonHandler_tb;

architecture testbench1 of buttonHandler_tb is

  -- component decleration

component buttonHandler
	port (
		buttonInput,clockInput : in std_logic; 
		simplePush,longPush : out std_logic
	);
end component;
	

  -- configuration
  for i_buttonHandler : buttonHandler use entity WORK.buttonHandler(buttonHandler_arch);

  -- internal signals
  signal buttonInput,simplePush,longPush, clockInput : std_logic := '0';
  constant period : time := 50 ns;

  begin --architecture

   
	i_buttonHandler : buttonHandler
	port map (
		buttonInput => buttonInput,
		clockInput  => clockInput,
		simplePush  => simplePush,
		longPush    => longPush
	);

	generate_clock : process (clockInput)
	begin -- process
    	clockInput <= NOT clockInput after period/2;
	end process;

	process 

 	begin
     	wait for 2*period + 66 ns;

		-- simple push case
		buttonInput <= '1';
		wait for period;
		buttonInput <= '0';	
		wait for period;

		-- long push case
		buttonInput <= '1';
		wait for 15 ms;
		buttonInput <= '0';
		wait for period;

		-- long push case
		buttonInput <= '1';
		wait for 15 ms;
		buttonInput <= '0';
		wait for period;
		
		-- simple push case
		buttonInput <= '1';
		wait for period;
		buttonInput <= '0';
		wait for period;

		-- simple push case
		buttonInput <= '1';
		wait for period;
		buttonInput <= '0';
		wait for period;
        
	   assert false report "simulation finished" severity note;
       wait;
	end process;	
end architecture;
